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DMA Control Registers 5–0 (DCR[5–0])
Table 4-11. DMA Control Register (DCR) Bit Definitions (Continued)
Bit
Number
15–11
Bit Name
DRS[4–0]
Reset
Value
0
DMA Request Source
Description
Encodes the source of DMA requests that trigger the DMA transfers. The DMA request
sources may be external devices requesting service through the IRQA, IRQB, IRQC and
IRQD pins, triggering by transfers done from a DMA channel, or transfers from the internal
peripherals. All the request sources behave as edge-triggered synchronous inputs.
DRS[4–0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111–11111
Requesting Device
External (IRQA pin)
External (IRQB pin)
External (IRQC pin)
External (IRQD pin)
Transfer done from channel 0
Transfer done from channel 1
Transfer done from channel 2
Transfer done from channel 3
Transfer done from channel 4
Transfer done from channel 5
ESSI0 receive data (RDF0 = 1)
ESSI0 transmit data (TDE0 = 1)
ESSI1 receive data (RDF1 = 1)
ESSI1 transmit data (TDE1 = 1)
SCI receive data (RDRF = 1)
SCI transmit data (TDRE = 1)
Timer0 (TCF0 = 1)
Timer1 (TCF1 = 1)
Timer2 (TCF2 = 1)
Host receive data full (HRDF = 1)
Host transmit data empty (HTDE = 1)
EFCOP input buffer empty (FDIBE=1)
EFCOP output buffer full (FDOBF=1)
Reserved
Peripheral requests 18–21 (DRS[4–0] = 111xx) can serve as fast request sources. Unlike a
regular peripheral request in which the peripheral can not generate a second request until
the first one is served, a fast peripheral has a full duplex handshake to the DMA, enabling a
maximum throughput of a trigger every two clock cycles. This mode is functional only in the
Word Transfer mode (that is, DTM = 001 or 101). In the Fast Request mode, the DMA sets
an enable line to the peripheral. If required, the peripheral can send the DMA a one cycle
triggering pulse. This pulse resets the enable line. If the DMA decides by the priority
algorithm that this trigger will be served in the next cycle, the enable line is set again, even
before the corresponding register in the peripheral is accessed.
10
D3D
0
Three-Dimensional Mode
Indicates whether a DMA channel is currently using three-dimensional (D3D = 1) or
non-three-dimensional (D3D = 0) addressing modes. The addressing modes are specified by
the DAM bits.
DSP56311 User’s Manual, Rev. 2
Freescale Semiconductor
4-31
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